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1 datasheet 40v 2.5a regulator with integrated high-side mosfet for synchronous buck or boost buck converter isl78201 the isl78201 is an aec-q100 qualified 40v, 2.5a synchronous buck or boost buck controller with a high-side mosfet and low-side driver integrated. in buck mode, the isl78201 supports a wide input range of 3v to 40v. in boost-buck mode, the input range can be extended down to 2.5v and output regulation can be maintained when v in drops below v out , enabling sensitive electronics to remain on during cold-cranking and start-stop applications. the isl78201 has a flexible selection of operation modes including forced pwm mode and an optional switch to pfm mode for light loads. in pfm mode, the quiescent input current is as low as 300a and can be further re duced to 180a with auxvcc connected to v out under 12v v in and 5v v out application. the load boundary between pfm and pwm can be programmed to cover wide applications. the low-side driver can be either used to drive an external low-side mosfet for a synchronous buck, or left unused for a standard non-synchronous buck. the low-side driver can also be used to drive a boost converter as a pre-re gulator that greatly expands the operating input voltage range down to 2.5v or lower (refer to ? typical application schematic iii - boost buck converters ? on page 5 ). the isl78201 offers the most robust current protections. it uses peak current mode control with cycl e-by-cycle current limiting. it is implemented with frequency foldback undercurrent limit condition; in addition, the hiccup overcurrent mode is also implemented to guarantee reliable operations under harsh short conditions. the isl78201 has comprehensive protections against various faults including overvoltage and over-temperature protections, etc. features ? buck mode: input voltage range 3v to 40v (refer to ? input voltage ? on page 15 for more details) ? boost mode expands operating input voltage lower than 2.5v (refer to ? input voltage ? on page 15 for more details) ? selectable forced pwm mode or pfm mode ? 300a ic quiescent current (pfm, no load); 180a input quiescent current (pfm, no load, v out tied to auxvcc) ? less than 5a (max) shutdown input current (ic disabled) ? operational topologies -synchronous buck -non-synchronous buck -two stage boost buck - non-inverting single inductor buck boost ? programmable frequency from 200khz - 2.2mhz and frequency synchronization capability ? 1% tight voltage regulation accuracy ? reliable cycle-by-cycle overcurrent protection - temperature compensated current sense - programmable oc limit - frequency foldback and hiccup mode protection ? 20 ld htssop package ? aec-q100 qualified ? pb-free (rohs compliant) applications ? automotive applications ? general purpose power regulator ? 24v bus power ?battery power ? embedded processor and i/o supplies figure 1. typical application figure 2. efficiency, synchronous buck, pfm mode, v out 5v, t a = +25c v out isl78201 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood 50 55 60 65 70 75 80 85 90 95 100 0.1m 1m 10m 100m 1 2.5 efficiency (%) load current (a) 6v v in 12v v in 24v v in 40v v in march 31, 2015 fn8615.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl78201 2 fn8615.1 march 31, 2015 submit document feedback pin configuration isl78201 (20 ld htssop) top view functional pin description pin name pin # description pgnd 1 this pin is used as the ground connec tion of the power flow including driver. boot 2 this pin provides bias voltage to the high-side mosfet driv er. a bootstrap circuit is used to create a voltage suitable to drive the internal n-channel mosfet. the boot char ge circuitries are integrated inside the ic. no external boot diode is needed. a 1f ceramic capacitor is recommended to be used between boot and phase pin. vin 3, 4 connect the input rail to these pins that are connected to the drain of the integrated hi gh-side mosfet, as well as the source for the internal linear regulator that provides the bias of the ic. range: 3v to 40v. with the part switching, the op erating input voltage applied to the vin pins must be under 40v. this recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding absolute maximum ratings. sgnd 5 this pin provides the return path for the control and monitor portions of the ic. vcc 6 this pin is the output of the internal linear regulator that supplies the bias fo r the ic including the driver. a minimum 4 .7f decoupling ceramic capacitor is recommended between vcc to ground. auxvcc 7 this pin is the input of the auxilia ry internal linear regulator which can be supplied by the regulator output after pow er-up. with such a configuration, the power dissipation inside the ic is reduced. the inpu t range for this ldo is 3v to 20v. in boost mode operation, this pin works as boost output overvo ltage detection pin. it detects the boost output through a resist or divider. when the voltage on this pin is above 0.8v, the boost pwm is disabled; and when voltag e on this pin is below 0.8v minus the hysteresis, the boost pwm is enabled. range: 3v to 20v. en 8 the controller is enabled when this pin is pulled high or le ft floating. the ic is disabled when this pin is pulled low. range: 0v to 5.5v. fs 9 to connect this pin to vcc, or gnd, or left open will forc e the ic to have 500khz switchin g frequency. the oscillator switch ing frequency can also be programmed by adjust ing the resistor from this pin to gnd. ss 10 connect a capacitor from this pin to ground. this capacitor, along with an internal 5a current source, sets the soft-start interval of the converter. also this pin can be used to track a ramp on this pin. fb 11 this pin is the inverting input of the voltage feedback error amplifier. with a pr operly selected resistor divider connecte d from v out to fb, the output voltage can be set to any voltage between the input rail (reduced by maximum duty cycle and voltage drop) and the 0.8v reference. loop compensation is achieved by connecting an rc network across comp and fb. the fb pin is also monitored for overvoltage events. comp 12 output of the voltage feedback error amplifier. ilimit 13 programmable current limit pin. with this pin connected to vcc pin, or to gnd, or left open, the current limit threshol d is set to default 3.6a; the current limit threshold can be programmed with a resistor from this pin to gnd. mode 14 mode selection pin. pull this pin to gnd for forced pwm mode ; to have it floating or connected to vcc will enable pfm mod e when the peak inductor current is belo w the default threshold of 700ma. the current boundary threshold between pfm and pwm can also be programmed with a resistor at this pin to ground. for more details on pf m mode operation refer to the ? functional description ? on page 14 . ext_boost phase pgood mode ilimit fb phase comp 11 12 13 14 15 16 17 18 lgate sync 19 20 pgnd boot vin vin sgnd vcc auxvcc en fs ss 1 2 3 4 5 6 7 8 9 10 21 pad
isl78201 3 fn8615.1 march 31, 2015 submit document feedback pgood 15 pgood is an open drain output and pull-up this pin with a resistor to vcc for proper function. pgood will be pulled low under the events when the output is out of regulation (ov or uv) or en pin is pulled low. pgood rising has a fixed 128 cycles delay. phase 16, 17 these pins are the phase nodes that should be connec ted to the output inductor. these pins are connected to the sour ce of the high-side n channel mosfet. ext_boost 18 this pin is used to set boost mode and monitor the ba ttery voltage that is the input of the boost converter. after v cc por, the controller will detect the voltage on this pin, if voltag e on this pin is below 200mv, the controller is set in synchronous/non-synchronou s buck mode and latch in this state unless vcc is below the por falling th reshold; if the voltage on this pin after vcc por is above 200mv, the contro ller is set in boost mode and latch in this state. in boost mode, this pin is used to monitor input voltage through a resistor divider. by setting the resistor divider, the high threshold and hysteresis can be programmed . when voltage on this pin is above 0. 8v, the pwm output (lgate) for the boost converter is disabled, and when voltage on this pin is below 0.8v minus the hysteres is, the boost pwm is enabled. in boost mode operation, pfm is disabled when boos t pwm is enabled. check b oost mode operation in the ? functional description ? on page 14 for more details. sync 19 this pin can be used to synchronize two or more isl78201 contro llers. multiple isl7 8201s can be synchr onized with their sync pins connected together. 180 degree phase shift is automatically generated between the master and slave ics. the internal oscillator can also lock to an external frequency source applied on th is pin with square pulse waveform (with frequency 10% higher than the ic?s local frequency, and puls e width higher than 150ns). this pin should be left floating if not used. range: 0v to 5.5v. lgate 20 in synchronous buck mode, this pin is used to drive the lower side mosfet to improve efficiency. a 5.1k or smaller value resistor has to be added to connect lgate to ground to avoid falsely turn-on of lgate caused by coupling noise. in non-synchronous buck when a diode is used as the bottom si de power device, this pin should be connected to vcc through a resistor (less than 5k) before vcc start-up to have low-side driver (lgate) disabled. in boost mode, it can be used to drive the boost power mosfet . the boost control pwm is the same with the buck control pwm. pad 21 bottom thermal pad. it is not connected to any electrical potent ial of the ic. in layout it mu st be connected to pcb ground copper plane with an area as large as possib le to effectively reduce the thermal impedance. functional pin description (continued) pin name pin # description ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL78201AVEZ 78201 avez -40 to +105 20 ld htssop m20.173a isl78201eval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl78201 . for more information on msl please see techbrief tb363 .
isl78201 4 fn8615.1 march 31, 2015 submit document feedback block diagram pgood ss fb boot phase (x2) current monitor mode sgnd en fs comp vcc vin 0.8v reference voltage monitor vin (x2) vcc pgnd auxvcc ocp, ovp, otp pfm logic boost mode control slope compensation lgate ilimit auxilary ldo ea comparator oscillator vcc 5a + + power-on reset soft-start logic sync ext_boost gate drive pfm/fpwm bias ldo boot refresh figure 3. block diagram
isl78201 5 fn8615.1 march 31, 2015 submit document feedback typical application schematic i figure 4a. synchronous buck fi gure 4b. non-synchronous buck typical application schematic ii - v cc switch over to v out figure 5a. synchronous buck fi gure 5b. non-synchronous buck typical application schematic iii - boost buck converters figure 6a. 2-stage boost buck figure 6b. non-inverting si ngle inductor buck boost v out isl78201 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out isl78201 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out isl78201 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out isl78201 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out isl78201 vcc sgnd mode boot vin phase pgnd fs pgood en ss fb comp auxvcc lgate ilimit + battery ext_boost sync r1 r2 r3 r4 + v out isl78201 vcc sgnd boot vin phase pgnd fs pgood en ss fb comp auxvcc ilimit ext_boost sync lgate v in vcc 1m 130k
isl78201 6 fn8615.1 march 31, 2015 submit document feedback absolute maximum rating s thermal information vin, phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +44v vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +6.0v auxvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +22v absolute boot voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0v upper driver supply voltage, v boot - v phase . . . . . . . . . . . . . . . . . . . +6.0v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vcc + 0.3v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . 2000v machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 250v charged device model (tested per aec-q100-011). . . . . . . . . . . . 1000v latch-up rating (tested per jesd78b; cl ass ii, level a) . . . . . . . . . 100ma thermal resistance ? ja (c/w) ? jc (c/w) htssop package ( notes 4 , 5 ) . . . . . . . . . . . . . . . 35 3.5 maximum junction temperature (plastic package) . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions supply voltage on vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 40v auxvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +20v ambient temperature range (automotive). . . . . . . . . . . . . . .-40c to +105c junction temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications refer to the block diagram ( page 4 ) and typical application schematics ( page 5 ). operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v, t a = -40c to +105c. typicals are at t a = +25c. boldface limits apply across the operatin g temperature range, -40c to +105c. parameter symbol test conditions min ( note 6 )typ max ( note 6 )units v in supply v in pin voltage range v in pin 3.05 40 v v in connected to vcc 3.05 5.5 v operating supply current i q mode = vcc/floating (pfm), no load at the output 300 a mode = gnd (forced pwm), v in = 12v, ic operating, not including driving current 1.3 ma shutdown supply current i in_sd en connected to gnd, v in = 12v 2.8 4.5 a internal main linear regulator main ldo v cc voltage v cc v in > 5v 4.2 4.5 4.8 v main ldo dropout voltage v dropout_main v in = 4.2v, i vcc = 35ma 0.3 0.52 v v in = 3v, i vcc = 25ma 0.25 0.42 v v cc current limit of main ldo 60 ma internal auxiliary linear regulator auxvcc input voltage range v auxvcc 320 v aux ldo v cc voltage v cc v auxvcc > 5v 4.2 4.5 4.8 v ldo dropout voltage v dropout_aux v auxvcc = 4.2v, i vcc = 35ma 0.3 0.52 v v auxvcc = 3v, i vcc = 25ma 0.25 0.42 v current limit of aux ldo 60 ma aux ldo switch-over rising threshold v auxvcc_rise auxvcc voltage rise, switch to auxiliary ldo 2.97 3.1 3.2 v aux ldo switch-over falling threshold v auxvcc_fall auxvcc voltage fall, switch back to main bias ldo 2.73 2.87 2.97 v aux ldo switch-over hysteresis v auxvcc_hys auxvcc switch-over hysteresis 0.2 v power-on reset rising v cc por threshold v porh_rise 2.82 2.9 3.05 v falling v cc por threshold v porl_fall 2.6 2.8 v
isl78201 7 fn8615.1 march 31, 2015 submit document feedback v cc por hysteresis v porl_hys 0.3 v enable required enable on voltage v enh 1.7 v required enable off voltage v enl 1 v en pull-up current i en_pullup v en = 1.2v, v in = 24v 1.5 a v en = 1.2v, v in = 12v 1.2 a v en = 1.2v, v in = 5v 0.9 a oscillator pwm frequency f osc r t = 665k 160 200 240 khz r t = 51.1k 1870 2200 2530 khz fs pin connected to vcc or floating or gnd 450 500 550 khz min on time t min_on 130 225 ns min off time t min_off 210 330 ns synchronization input high threshold vih 2 v input low threshold vil 0.5 v input minimum pulse width 25 ns input impedance 100 k input minimum frequency divided by free running frequency 1.1 input maximum frequency divided by free running frequency 1.6 output pulse width c sync = 100pf 100 ns output pulse high voh r load = 1k vcc- 0.25 v output pulse low vol gnd v reference voltage reference voltage v ref 0.8 v system accuracy -1.0 1.0 % fb pin source current 5na soft-start soft-start current i ss 3 5 7 a error amplifier unity gain-bandwidth c load = 50pf 10 mhz dc gain c load = 50pf 88 db maximum output voltage 3.6 v minimum output voltage 0.5 v slew rate sr c load = 50pf 5 v/s pfm mode control electrical specifications refer to the block diagram ( page 4 ) and typical application schematics ( page 5 ). operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v, t a = -40c to +105c. typicals are at t a = +25c. boldface limits apply across the operating temp erature range, -40c to +105c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )units
isl78201 8 fn8615.1 march 31, 2015 submit document feedback default pfm current threshold mode = vcc or floating 700 ma internal high-side mosfet upper mosfet r ds(on) r ds(on)_up ( note 7 ) limits apply for +25c 127 140 m low-side mosfet gate driver lgate source resistance 100ma source current 3.5 lgate sink resistance 100ma sink current 2.8 boost converter control ext_boost boost_turn-off threshold voltage 0.74 0.8 0.86 v ext_boost hysteresis sink current i ext_boost_hys 2.1 3.2 4.2 a auxvcc boost turn-off threshold voltage 0.74 0.8 0.86 v auxvcc hysteresis sink current i auxvcc_hys 2.1 3.2 4.2 a power good monitor overvoltage rising trip point v fb/ v ref percentage of reference point 104 110 116 % overvoltage rising hysteresis v fb/ v ovtrip percentage below ov trip point 3 % undervoltage falling trip point v fb/ v ref percentage of reference point 84 90 96 % undervoltage falling hysteresis v fb/ v uvtrip percentage above uv trip point 3 % pgood rising delay t pgoodr_delay 128 cycle pgood leakage current pgood high, v pgood = 4.5v 10 na pgood low voltage v pgood pgood low, i pgood = 0.2ma 0.10 v overcurrent protection default cycle-by-cycle current limit threshold i oc_1 ilimit = gnd or vcc or floating 3 3.6 4.2 a hiccup current limit threshold i oc_2 hiccup, i oc_2 /i oc_1 115 % overvoltage protection ov 120% trip point active in and after soft-start percentage of reference point lg = ug = low 120 % ov 120% release point active in and after soft-start percentage of reference point 102.5 % ov 110% trip point active after soft-start done percentage of reference point lg = ug = low 110 % ov 110% release point active after soft-start done percentage of reference point 102.5 % over-temperature protection over-temperature trip point 160 c over-temperature recovery threshold 140 c notes: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 7. wire bonds included. electrical specifications refer to the block diagram ( page 4 ) and typical application schematics ( page 5 ). operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v, t a = -40c to +105c. typicals are at t a = +25c. boldface limits apply across the operating temp erature range, -40c to +105c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )units
isl78201 9 fn8615.1 march 31, 2015 submit document feedback performance curves figure 7. efficiency, synchronous buck, forced pwm mode, 500khz, v out 5v, t a = +25c figure 8. efficiency, synchronous buck, pfm mode, v out 5v, t a = +25c figure 9. line regulation, v out 5v, t a = +25c figure 10. load regulation, v out 5v, t a = +25c figure 11. efficiency, sync hronous buck, forced pwm mode, 500khz, v out 3.3v, t a = +25c figure 12. efficiency, synchronous buck, pfm mode, v out 3.3v, t a = +25c 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 load current (a) 12v v in 24v v in 40v v in 6v v in efficiency (%) 2.5 50 55 60 65 70 75 80 85 90 95 100 0.1m 1m 10m 100m 1 2.5 efficiency (%) load current (a) 6v v in 12v v in 24v v in 40v v in 4.950 4.952 4.954 4.956 4.958 4.960 4.962 4.964 4.966 4.968 4.970 0 5 10 15 20 25 30 35 40 45 50 input voltage (v) v out (v) i o = 2a i o = 0a i o = 1a 4.950 4.952 4.954 4.956 4.958 4.960 4.962 4.964 4.966 4.968 4.970 0.0 0.5 1.0 1.5 2.0 2.5 load current (a) 6v v in 12v v in 24v v in 40v v in v out (v) 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 2.5 efficiency (%) load current (a) 6v v in 12v v in 24v v in 40v v in 1m 10m 100m 1 2.5 load current (a) efficiency (%) 0.1m 6v v in 12v v in 24v v in 40v v in 40 45 50 55 60 65 70 75 80 85 90 95 100
isl78201 10 fn8615.1 march 31, 2015 submit document feedback figure 13. input quiescent current under no load, pfm mode, auxvcc connected to v out , v out = 5v figure 14. ic die temperat ure under +105c ambient temperature, 100 cfm, 500khz, v out = 5v, i o = 2a figure 15. ic die temper ature under +25c ambient temperature, still air, 500khz, i o = 2a figure 16. ic die temperature under +25c ambient temperature, still air, 500khz, v out = 9v figure 17. upper mosfet r ds(on) (m ? ) over temperature performance curves (continued) 0 20 40 60 80 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125 input current (a) ambient temperature (c) v in = 40v v in = 24v v in = 12v 105 110 115 120 125 130 135 140 145 150 0 5 10 15 20 25 30 35 40 45 50 ic die temperature (c) v in (v) 25 30 35 40 45 50 55 60 65 70 75 80 85 0 5 10 15 20 25 30 35 40 45 50 v in (v) ic die temperature (c) v out = 5v v out = 12v v out = 20v v out = 9v 25 30 35 40 45 50 55 60 65 70 75 80 85 1.0 1.5 2.0 2.5 i out (a) ic die temperature (c) v in = 40v v in = 12v v in = 24v 190 160 150 140 130 120 110 100 -50 -20 -40 -30 -10 10 20 30 40 50 60 70 80 90 100 110 120 0 die temperature (c) upper mosfet r ds(on) (m) 180 170 130
isl78201 11 fn8615.1 march 31, 2015 submit document feedback figure 18. synchronous buck mode, v in 36v, i o 2a, enable on figure 19. synchronous buck mode, v in 36v, i o 2a, enable off figure 20. v in 36v, prebiased start-up figure 21. synchronous buck with force pwm mode, v in 36v, i o 2a figure 22. v in 24v, 0 to 2a step load, force pwm mode figure 23. v in 24v, 80ma load, pfm mode performance curves (continued) v out 2v/div 2ms/div phase 20v/div v out 2v/div 2ms/div phase 20v/div v out 2v/div 2ms/div phase 20v/div v out 20mv/div (5v offset) phase 20v/div 5s/div v out 100mv/div (5v offset) i out 1a/div phase 20v/div 1ms/div v out 1v/div 100s/div v out 70mv/div (5v offset) phase 20v/div lgate 5v/div
isl78201 12 fn8615.1 march 31, 2015 submit document feedback figure 24. v in 24v, 0 to 2a step load, pfm mode figure 25. non-synchronous buck, force pwm mode, v in 12v, no load figure 26. non-synchronous buck, force pwm mode, v in 12v, 2a figure 27. boost buck mode, boost input step from 40v to 3v figure 28. boost buck mode, boost input step from 3v to 40v figure 29. boost buck mode, v o = 9v, i o = 1.8a, boost input drops from 16v to 9v dc performance curves (continued) v out 200mv/div (5v offset) lgate 5v/div i out 1a/div phase 20v/div 1ms/div v out 10mv/div (5v offset) phase 5v/div 20s/div v out 10mv/div (5v offset) phase 10v/div 5s/div v out 1v/div v in _boost 5v/div 20ms/div v out 1v/div v in _boost 5v/div 20ms/div v out 5v/div phase_boost 20v/div 10ms/div il_boost 2a/div phase_buck 20v/div
isl78201 13 fn8615.1 march 31, 2015 submit document feedback figure 30. efficiency, boost buck, 500khz, v out 12v, t a = +25c performance curves (continued) 50 55 60 65 70 75 80 85 90 95 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 load current (a) 15v v in 30v v in 9v v in 6v v in 5v v in boost buck, v o = 12v efficiency (%)
isl78201 14 fn8615.1 march 31, 2015 submit document feedback functional description initialization initially, the isl78201 continually monitors the voltage at en pin. when the voltage on en pin exceeds its rising threshold, the internal ldo will start-up to build up v cc . after power-on reset (por) circuits detect that v cc voltage has exceeded the por threshold, the soft-start will be initiated. soft-start the soft-start (ss) ramp is built up in the external capacitor on the ss pin that is charged by an internal 5a current source. the ss ramp starts from 0v to a voltage above 0.8v. once ss reaches 0.8v, the bandgap reference takes over and the ic goes into steady state operation. the so ft-start time is referring to the duration for ss pin ramps from 0 to 0.8v while output voltage ramps up with the same rate from 0 to target regulated voltage. the required capacitance at ss pin can be calculated from equation 1 . the ss plays a vital role in the hiccup mode of operation. the ic works as cycle-by-cycle peak current limiting at overload condition. when a harsh condition occurs and the current in the upper side mosfet re aches the second overcurrent threshold, the ss pin is pulled to ground and a dummy soft-start cycle is initiated. at the dummy ss cycle, the current to charge the soft-start cap is cut down to 1/5 of its normal value. therefore, a dummy ss cycle takes 5 times that of the regular ss cycle. during the dummy ss period, the control loop is disabled and no pwm output. at the end of this cy cle, it will start the normal ss. the hiccup mode persists until the second overcurrent threshold is no longer reached. the isl78201 is capable of start-up with prebiased output. pwm control pulling the mode pin to gnd will set the ic in forced pwm mode. the isl78201 employs the peak current mode pwm control for fast transient response and cycl e-by-cycle current limiting. see ? block diagram ? on page 4 . the pwm operation is initialized by the clock from the oscillator. the upper mosfet is turned on by the clock at the beginning of a pwm cycle and the current in th e mosfet starts to ramp up. when the sum of the current sense signal and the slope compensation signal reaches the error amplifier output voltage level, the pwm comparator is triggered to shut down the pwm logic to turn off the high-side mosfet. the high-side mosfet stays off until the next clock signal comes for the next cycle. the output voltage is sensed by a resistor divider from v out to the fb pin. the difference between the fb voltage and 0.8v reference is amplified and compensated to generate the error voltage signal at the comp pin. then the comp pin signal is compared with the current ramp signal to shut down the pwm. pfm mode operation to pull the mode pin high (>2.5v) or leave the mode pin floating will set the ic to have pfm (pulse frequency modulation) operation in light load. in pfm mode, the switching frequency is dramatically reduced to minimize the switching loss. the isl78201 enters pfm mode when the mosfet peak current is lower than the pwm/pfm boundary current threshold. this threshold is 700ma as default when there is no programming resistor at mode pin. it can also be programmed by a resistor at the mode pin to ground (see equation 2 ). where ipfm is the desired pwm/pfm boundary current threshold and r mode is the programming resistor. the usable resistor value range to program pfm current threshold is 150k to 200k . r mode value out of this range is not recommended. synchronous and non-synchronous buck the isl78201 supports both synchronous and non-synchronous buck operations. in synchronous buck configuration, a 5.1k or smaller value resistor has to be added to connect lgate to ground to avoid falsely turn-on of lgate caused by coupling noise. for a non-synchronous buck operation when a power diode is used as the low-side power device, the lgate driver can be disabled with lgate connected to vcc (before ic start-up). for non-synchronous buck, the phase node will show oscillations after high-side turns off (as shown in figure 24 - blue trace). this is normal due to the oscillations among the parasitic capacitors at phase node and output inductor. a rc snubber (suggesting 200 and 2.2nf as typical) at phase node can reduce this ringing. auxvcc switch-over the isl78201 has an auxiliary ldo integrated as shown in the block diagram on page 4 . it is used to replace the internal main ldo function after the ic start-up. ? typical application schematic ii - v cc switch over to v out ? on page 5 shows its basic application setup with output voltage connected to auxvcc. after ic soft-start done and the output voltage is built up to steady c ss ? f ?? 6.5 t ss s ?? ? = (eq. 1) r mode 118500 ipfm 0.2 + ---------------------------- - = (eq. 2) figure 31. r mode vs ipfm 150 160 170 180 190 200 0.3 0.4 0.5 0.6 0.7 r mode (k) i pfm (a)
isl78201 15 fn8615.1 march 31, 2015 submit document feedback state, once the auxvcc pin voltage is over the aux ldo switch- over rising threshold, the main ldo is shut off and the auxiliary ldo is activated to bias vcc. since the auxvcc pin voltage is lower than input voltage v in , the internal ldo dropout voltage and the consequent power loss is reduced. this feature brings substantial efficiency improvements in light load range especially at high input voltage applications. when the voltage at auxvcc falls below the aux ldo switch-over falling threshold, the auxiliary ldo is shut off and the main ldo is re-activated to bias vcc. at the ov/uv fault events, the ic also switch over back from auxiliary ldo to main ldo. the auxvcc switchover function is offered in buck configuration. it is not offered in boost configuration when the auxvcc pin is used to monitor the boost output voltage for ovp. input voltage with the part switching, the operating isl78201 input voltage must be under 40v. this recommendation allows for short voltage ringing spikes (within a co uple of ns time range) due to part switching while not exceeding 44v as absolute maximum ratings. the lowest ic operating input voltage (vin pin) depends on vcc voltage and the rising and falling v cc por threshold in electrical specifications table on page 6 . at ic start-up when v cc is just over rising por threshold, there is no switching yet before the soft-start starts. so the ic minimum start-up voltage on vin pin is 3.05v (max of rising v cc por). when the soft-start is initiated, the regulator is switching and the dropout voltage across the internal ldo increases due to driving current. thus the ic vin pin shutdown voltage is related to driving current and v cc por falling threshold. the inte rnal upper side mosfet has typical 10nc gate drive. for a typical example of synchronous buck with 4nc lower mosfet gate drive and 500khz switching frequency, the driving current is 7ma total causing 70mv drop across internal ldo under 3v vin. then the ic shut down voltage on vin pin is 2.87v (2.8v+0.07v). in practical design, extra room should be taken into account with concerns of voltage spikes at vin. with boost buck configuration, the input voltage range can be expanded further down to 2.5v or lower depending on the boost stage voltage drop upon maximum duty cycle. since the boost output voltage is connected to vin pin as the buck inputs, after the ic starts up, the ic will keep operating and switching as long as the boost output voltage can keep the vcc voltage higher than falling threshold. refer to ? boost converter operation ? on page 15 for more details. output voltage the output voltage can be programmed down to 0.8v by a resistor divider from v out to fb. for buck, the maximum achievable voltage is (v in * d max - v drop ), where v drop is the voltage drop in the power path including mainly the mosfet r ds(on) and inductor dcr. the maximum duty cycle d max is decided by (1 - fs * t min(off) ). output current with the high-side mosfet integrated, the maximum current isl78201 can support is decided by the package and many operating conditions in cluding input voltage, output voltage, duty cycle, switching frequency and temperature, etc. from the thermal perspective, the die temperature shouldn?t be above +125c with the power loss dissipated inside of the ic. figures 14 through 16 show the thermal performance of this part operating in buck at different conditions. the part can output 2.5a under typical buck application condition v in 8~36v, v o 5v, 500khz, still air and + 85c ambient conditions. the output current should be derated under any conditions causing the die temperature to exceed +125c. figure 14 shows a 5v, 2a output application over v in range under +105c ambient temperat ure with 100 cfm air flow. figure 15 shows 2a applications unde r +25c still air conditions. different v out (5v, 9v, 12v, 20v) app lications thermal data are shown over v in range at +25c and still air. the temperature rise data in this figure can be used to estimate the die temperature at different ambient temperatures under various operating conditions. note: more temperature rise is expected at higher ambient temperatures due to more conduction loss caused by r ds(on) increase. figure 16 shows thermal performance under various output currents and input voltages. it shows the temperature rise trend with load and v in changes. basically, the die temperature equals the sum of ambient temperature and the temperature rise resulting from power dissipated from the ic package with a certain junction to ambient thermal impedance ? ja . the power dissipated in the ic is related to the mosfet switch ing loss, conduction loss and the internal ldo loss. besides the load, these losses are also related to input voltage, output voltage, duty cycle, switching frequency and temperature. with the exposed pad at the bottom, the heat of the ic mainly goes through the bottom pad and ? ja is greatly reduced. the ? ja is highly related to layout and air flow conditions. in layout, multiple vias (20) are strongly recommended in the ic bottom pa d. in addition, the bottom pad with its vias should be placed in ground copper plane with an area as large as possible connected through multiple layers. the ? ja can be reduced further with air flow. for applications with high ou tput current and bad operating conditions (compact board size, hi gh ambient temperature, etc.), synchronous buck is highly reco mmended since the external low- side mosfet generate s smaller heat than external low-side power diode. this helps to reduce pcb temperature rise around the isl78201 and less junction temperature rise. boost converter operation the typical application schematic iii on page 5 shows the circuits where the boost works as a pre-stage to provide input to the following buck stage. this is for applications when the input voltage could drop to a very low voltage in some constants (in some battery powered systems as an example), causing the output voltage drops out of regulation. the boost converter can be enabled to boost the input voltage up to keep the output voltage in regulation. when the system input voltage recovers back to normal, the boost stage is disabled while only the buck stage is switching.
isl78201 16 fn8615.1 march 31, 2015 submit document feedback ext_boost pin is used to set boost mode and monitor the boost input voltage. at ic start-up befo re soft-start, the controller will latch in boost mode when the voltage on this pin is above 200mv; it will latch in synchronous buck mode if voltage on this pin is below 200mv. in boost mode, the low-side driver output pwm has the same pwm signal with the buck regulator. in boost mode, the ext_boost pi n is used to monitor boost input voltage to turn on and turn off the boost pwm. the auxvcc pin is used to monitor the boost output voltage to turn on and turn off the boost pwm. referring to figure 32 , a resistor divider from boost input voltage to the ext_boost pin is used to detect the boost input voltage. when the voltage on the ext_boost pin is below 0.8v, the boost pwm is enabled with a fixed 500s soft-start when the boost duty cycle increases from t minon *fs to ~50% and a 3a sinking current is enabled at the ext_boost pin for hysteresis purposes. when the voltage on the ext_boost pin recovers to above 0.8v, the boost pwm is disabled immediately. use equation 3 to calculate the upper resistor r up (r1 in figure 32 ) for a desired hysteresis vhys at boost input voltage. use equation 4 to calculate the lower resistor r low (r2 in figure 32 ) according to a desired boost enable threshold. where vfth is the desired falling threshold on boost input voltage to turn on the boost, 3a is the hysteresis current, and 0.8v is the reference voltage to be compared. note the boost start-up threshold has to be selected in a way that the buck is operating well at cl ose loop before boost start-up. otherwise, large inrush current at boost start-up could occur at boost input due to the buck loop saturation. the boost startup input voltage threshold should be set high enough to cover the dc voltage drop of boost induct or and diode, also the buck?s maximum duty cycle and voltage conduction drop. this ensures buck is not reaching maximum duty cycle before boost startup . similarly, a resistor divider from boost output voltage to the auxvcc pin is used to detect the boost output voltage. when the voltage on auxvcc pin is below 0.8v, the boost pwm is enabled with a fixed 500s soft-start, and a 3a sinking current is enabled at auxvcc pin for hysteresis purpose. when the voltage on the auxvcc pin recovers to above 0.8v, the boost pwm is disabled immediately. use equation 3 to calculate the upper resistor r up (r3 in figure 32 ) according to a desired hysteresis vhy at boost output voltage. use equation 4 to calculate the lower resistor r low (r4 in figure 32 ) according to a desired boost enable threshold at boost output. assuming vbat is the boost input voltage, v outbst is the boost output voltage and v out is the buck output voltage, the steady state transfer functions are: from equations 5 and 6 , equation 7 can be derived to estimate the steady state boost output volt age as a function of vbat and vout: after the ic starts up, the boost buck converters can keep working when the battery voltage drops extremely low because the ic?s bias (vcc) ldo is powered by the boost output. for an example of 3.3v output application, when the battery drops to 2v, the vin pin voltage is powered by the boost output voltage that is 5.2v ( equation 7 ), meaning the vin pin (buck input) still needs 5.2v to keep the ic working. note in the above mentioned case, the boost input current could be high because the input voltage is very low r up m ? ?? vhys 3 ? a ?? --------------- - = (eq. 3) r low r up 0.8 ? vfth 0.8 C ---------------------------- = (eq. 4) figure 32. boost converter control auxvcc lgate + battery ext_boost + logic pwm lgate drive 0.8v 0.8v i_hys = 3a i_hys = 3a vout_bst r3 r4 r1 r2 C ------------ - vbat ? = (eq. 5) v out dv outbst ? d 1d C ------------ - vbat ? == (eq. 6) v outbst vbat vout + = (eq. 7)
isl78201 17 fn8615.1 march 31, 2015 submit document feedback (v in *i in =v out *i out / efficiency). if the design is to achieve the low input operation with full load, the inductor and mosfet have to be selected to have enough current ratings to handle the high current appearing at boost input. the boost inductor current are the same with the boost input curr ent, which can be estimated in equation 8 , where p out is the output power, vbat is the boost input voltage, and eff is the estimated efficiency of the whole boost and buck stages. based on the same concerns of boost input current, the start-up sequence must follow the rule th at the ic is enabled after the boost input voltage rise above a certain level. the shutdown sequence must follow the rule that the ic is disabled first before the boost input power source is turned off. at boost mode applications where there is no external control signal to enable/disable the ic, an external input uvlo circuit must be implemented for the start-up and shutdown sequence. pfm is not available in boost mode. non-inverting single inductor buck boost converter operation in ? typical application schematic iii - boost buck converters ? on page 5 , schematic (b) shows non-inverting single inductor buck boost configuration. the recommen ded setting is to use resistor divider 1m and 130k (as shown in ? typical application schematic iii - boost buck converters ? on page 5 (b) connecting from vcc to both ext_boost and auxvcc pins (ext_boost and auxvcc pin are directly connected). in this way, the ext_boost pin voltage is a fixed voltage 0.52v that is higher than the boost mode detection threshold 0.2v to set ic in boost mode and lower than the boost switching thresh old 800mv to have boost being constantly switching (during and after soft-start). as the same in 2-stage boost buck mode, lgate is switching on with the same phase of upper fe ts switching on, meaning both upper and lower side fets are on and off at the same time with the same duty cycle. when both fets on, input voltage charges inductor current ramping up for duration of dt; when both fets off, inductor current is free wheeling through the 2 power diodes to output, and output voltage discharge the inductor current ramping down for (1-d)t (in ccm mode). the steady state dc transfer function is: where v in is the input voltage, v out is the buck boost output voltage, d is duty cycle. another useful equation is to calculate the inductor dc current as shown in equation 10 : where il dc is the inductor dc current and i out is the output dc current. equation 10 says the inductor current is charging output only during (1-d)t, which means inductor current has larger dc current than output load current. so for this part with high side fet integrated, the non-inverting buck boost configuration has less load current capability compared with buck and 2-stage boost buck configurations. its load current capability depends mainly on the duty cycle and inductor current. inductor ripple current can be calculated below: the inductor peak current is, in power stage dc calculations, use equation 9 to calculate d, then use equation 10 to calculate il dc . d and il dc are useful information to estimate the hi gh side fet?s power losses and check if the part can meet the load current requirements.. oscillator and synchronization the oscillator has a default freque ncy of 500khz with the fs pin connected to vcc, ground, or floating. the frequency can be programmed to any frequency be tween 200khz and 2.2mhz with a resistor from the fs pin to gnd. the sync pin is bi-directional an d it outputs the ic?s default or programmed local clock signal when it?s free running. the ic locks to an external clock injected to sync pin (external clock frequency recommended to be 10% higher than the free running frequency). the delay from the rising edge of the external clock signal to the phase rising edge is half of the free running switching period pulse 220ns, (0.5tsw+220ns ). the maximum external clock frequency is recommended to be 1. 6 of the free running frequency. when the part enters pfm pulse skipping mode, the synchronization function is shut off and also no clock signal output in sync pin. with the sync pins simply connected together, multiple isl78201s can be synchronized. the slave ics automatically have 180 phase shift respect to the master ic. il in p out vbat eff ? ----------------------------- = (eq. 8) (eq. 9) v out d 1d C ------------------ v in ? = il dc 1 1d C ------------------ i out ? = (eq. 10) il ripple v out 1d C ?? t l ------------------------------------------------- = (eq. 11) il peak il dc 1 2 ---- il ripple ? + = (eq. 12) figure 33. r fs vs frequency 0 400 1200 0 1000 1500 2500 r fs (k) f s (khz) 1000 800 600 200 500 2000 r fs k ? ?? 145000 16 fs ? khz ?? C fs khz ?? ------------------------------------------------------------- - = (eq. 13)
isl78201 18 fn8615.1 march 31, 2015 submit document feedback pgood the pgood pin is output of an open drain transistor (refer to at ? block diagram ? on page 4 ). an external resistor is required to be pulled up to vcc for proper pgood function. at startup, pgood will be turned high (internal pgood open drain transistor is turned off) with 128 cycles delay after soft start is finished (soft start ramp reaches 1.02v) and fb voltage is within ov/uv window (90%ref isl78201 19 fn8615.1 march 31, 2015 submit document feedback for the ceramic capacitors (low esr): where ? i is the inductor?s peak to peak ripple current, f sw is the switching frequency and c out is the output capacitor. if using electrolytic capacitors then: regarding transient response needs, a good starting point is to determine the allowable overshoot in v out if the load is suddenly removed. in this case, energy stored in the inductor will be transferred to c out causing its voltage to rise. after calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. the equation 17 determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. where v outmax /v out is the relative maximum overshoot allowed during the removal of the load. input capacitors - buck depending upon the system input power rail conditions, the aluminum electrolytic type capacitor is normally needed to provide the stable input voltag e and restrict the switching frequency pulse current in small areas over the input traces for better emc performance. the input capacitor should be able to handle the rms current from the switching power devices. ceramic capacitors must be used at the vin pin of the ic and multiple capacitors including 1f and 0.1f are recommended. place these capacitors as closely as possible to the ic. output inductor - buck the inductor value determines the converter?s ripple current. choosing an inductor current re quires a somewhat arbitrary choice of ripple current, ? i. a reasonable starting point is 30% to 40% of total load current. the inductor value can then be calculated using equation 18 : increasing the value of inductan ce reduces the ripple current and thus ripple voltage. however, the larger inductance value may reduce the converter?s response time to a load transient. the inductor current rating should be such that it will not saturate in overcurrent conditions. low-side power mosfet in synchronous buck application, a power n mosfet is needed as the synchronous low-side mosfet and a good one should have low qgd, low r ds(on) and small rg (rg_typ < 1.5 recommended ) . vgth_min is recommended to be or higher than 1.2v. a good example is sqs462en. a 5.1k or smaller value resistor has to be added to connect lgate to ground to avoid falsely turn-on of lgate caused by coupling noise. output voltage feedback resistor divider the output voltage can be programmed down to 0.8v by a resistor divider from v out to fb according to equation 19 . in applications requiring the least input quiescent current, large resistors should be used for th e divider to keep its leakage current low. generally, a resistor value of 10k to 300k can be used for the upper resistor. boost inductor besides the need to sustain the current ripple to be within a certain range (30% to 50%), the boost inductor current at its soft-start is a more important perspective to be considered in selection of the boost inductor. each time the boost starts up, there is a fixed 500s soft-start time when the duty cycle increase linearly from t minon to ~50%. before and after boost start-up, the boost output voltage will jump from v in _boost to voltage (v in _boost + v out _buck). the design target in boost soft-start is to ensure the boost input current is sustained to a minimum but capable of charging the boost output voltage to have a voltage step equaling to v out _buck. a big inductor will block the inductor current increase and not high enough to be able to charge the output capacitor to the final steady state value (v in _boost+v out _buck) within 500s. a 6.8h inductor is a good starting point for its selection in design. the boost inductor current at start-up must be checke d by an oscilloscope to ensure it is under the acceptable range. it is suggested to run the isim model simulation to select the proper inductor value. boost output capacitor based on the same theory in boost start-up described above in boost inductor selection, a large capacitor at boost output will cause high inrush current at boos t pwm start-up. 22f is a good choice for applications with buck output voltage less than 10v. also, some minimum amount of capacitance has to be used in boost output to keep the system stable. it is suggested to run the isim model simulation to select the proper inductor value. loop compensation design-buck the isl78201 uses constant frequency peak current mode control architecture to achieve fa st loop transient response. an accurate current sensing pilot device in parallel with the upper mosfet is used for peak current control signal and overcurrent protection. the inductor is not considered as a state variable since its peak current is cons tant, and the system becomes single order system. it is much easier to design the compensator to stabilize the loop compared wi th voltage mode control. peak current mode control has inherent input voltage feed-forward function to achieve go od line regulation. figure 35 shows the small signal model of a buck regulator. v outripple ? i 8 ? f sw ? c out --------------------------------- - = (eq. 15) v outripple ? i*esr = (eq. 16) (eq. 17) c out i out 2 * l v out 2 * v outmax v out ? ?? 2 1 ? C --------------------------------------------------------------- --------------------- - = C fs ? i ? --------------------------- - v out v in ------------ - ? = --------------- + ?? ?? ?? ? = (eq. 19)
isl78201 20 fn8615.1 march 31, 2015 submit document feedback pwm comparator gain f m the pwm comparator gain f m for peak current mode control is given by equation 20 : where s e is the slew rate of the slope compensation and s n is given by equation 21 where r t is the gain of the current amplifier. current sampling transfer function h e (s) in current loop, the current sign al is sampled every switching cycle. it has the following transfer function in equation 22 : where q n and ? n are given by power stage transfer functions transfer function f 1 (s) from control to output voltage is: where transfer function f 2 (s) from control to inductor current is given by equation 24 : where . current loop gain t i (s) is expressed as equation 25 : the voltage loop gain with open current loop is equation 26 : the voltage loop gain with current loop closed is given by equation 27 : if t i (s)>>1, then equation 27 can be simplified as equation 28 : equation 28 shows that the system is a single order system. therefore, a simple type ii compensator can be easily used to stabilize the system. while type iii compensator is needed to expand the bandwidth for current mode control in some cases. a compensator with 2 zeros and 1 pole is recommended for this part as shown in figure 36 . its transfer function is expressed as equation 29 : where , compensator design goal: loop bandwidth f c : gain margin: >10db d v in d i l in in i l + 1:d + l i co rc -av(s) d comp v r t fm he(s) + t i (s) o v t v (s) i l p + 1:d + rc ro -av(s) r t fm he(s) t i (s) o t(s) ^ ^ v ^ ^ ^ ^ ^ ^ figure 35. small signal model of buck regulator r lp gain (vloop (s(fi)) ? v ? comp ---------------- 1 s e s n + ?? t s ----------------------------- - == (eq. 20) s n r t v in v o C l p ------------------- - = (eq. 21) h e s ?? s 2 ? n 2 ------ - = s ? n q n -------------- 1 ++ (eq. 22) q n 2 ? --- C = ? n ? f s = ? ?? v ? o d ? ----- - v in 1 s ? esr ----------- - + s 2 ? o 2 ------ - s ? o q p -------------- 1 ++ -------------------------------------- == (eq. 23) ? esr 1 r c c o ------------ - q p r o c o l p ----- - ? o 1 l p c o ---------------- - = , ? , = ? z 1 r o c o ------------- = ?? i ? o d ? ---- v in r o r lp + ---------------------- - 1 s ? z ------ + s 2 ? o 2 ------ - s ? o q p ------------- - 1 ++ -------------------------------------- == (eq. 24) t i s ?? r t f m f 2 s ?? h e s ?? = (eq. 25) t v s ?? kf m f 1 s ?? a v s ?? = (eq. 26) l v s ?? t v s ?? 1t i s ?? + ---------------------- - = (eq. 27) l v s ?? r o r lp + r t ---------------------- - 1 s ? esr ----------- - + 1 s ? p ------ - + --------------------- - a v s ?? h e s ?? --------------- ? p 1 r o c o ------------- ? , = (eq. 28) figure 36. type iii compensator r2 c1 r1 r bias r3 c3 v o v comp v ref a v s ?? v ? comp v ? o ---------------- 1 sr 1 c 1 ----------------- - 1 s ? cz1 ------------ + ?? ?? 1 s ? cz2 ------------ + ?? ?? 1 s ? cp --------- - + ?? ?? -------------------------------------------------------- - = = (eq. 29) ? cz1 1 r 2 c 1 ------------- - ? cz2 1 r 1 r 3 + ?? c 3 -------------------------------- = ? cp ? 1 r 3 c 3 ------------- - = , = -- - to 1 10 ------ - ?? ?? f s
isl78201 21 fn8615.1 march 31, 2015 submit document feedback phase margin: 45 the compensator design procedure is as follows: 1. position ? cz2 and ? cp to derive r3 and c3. put the compensator zero ? cz2 at (1 to 3)/(r o c o ) put the compensator pole ? cp at esr zero or 0.35 to 0.5 times of switching frequency, whichever is lower. in all-ceramic-cap design, the esr zero is normally higher than half of the switching frequency. r3 and c3 can be derived as following: case a: esr zero less than (0.35 to 0.5)f s case b: esr zero larger than (0.35 to 0.5)f s case c: derive at r2 and c1. the loop gain l v (s) at cross over frequency of f c has unity gain. therefore, c1 is determined by equation 35 . the compensator zero ? cz1 can boost the phase margin and bandwidth. to put ? cz1 at 2 times of cross cover frequency f c is a good start point. it can be adjusted according to specific design. r1 can be derived from equation 36 . example: v in = 12v, v o = 5v, i o = 2a, f s = 500khz, c o = 60f/3m ? , l = 10h, r t = 0.20v/a, f c = 50khz, r 1 = 105k, r bias =20k ? . select the crossover frequency to be 35khz. since the output capacitors are all ceramics, use equations 33 and 34 to derive r3 to be 20k and c3 to be 470pf. then use equations 35 and 36 to calculate c 1 to be 180pf and r 2 to be 12.7k. select 150pf for c 1 and 15k for r 2 . there is approximately 30pf parasitic capacitance between comp to fb pins that contributes to a high frequency pole. any extra external capacitor is not recommended between comp and fb. figure 37 shows the simulated bode plot of the loop. it is shown that it has 26khz loop bandwi dth with 70 phase margin and -28db gain margin. note in applications where the pfm mode is desired especially when type iii compensation netw ork is used, the value of the capacitor between the comp pin and the fb pin (not the capacitor in series with the resistor between comp and fb) should be minimal to reduce the noise coupling for proper pfm operation. no external capacitor between comp and fb is recommended at pfm applications. in pfm mode operations, a rc filter from fb to ground (r in series with c, connecting from fb to ground) may help to reduce the noise effects injected to fb pin. the recommended values for the filter is 499 to 1k for the r and 470pf for the c. loop compensation design for 2-stage boost buck and single-stage buck boost for 2-stage boost buck and single-stage non-inverting buck boost configurations, it?s highly recommended to use the isim model (the isl78200 isim model can be used to simulate isl78201 and it?s available through internet) to evaluate the loop bandwidth and phase margin. ? cz2 3 r o c o ------------- = (eq. 30) 1 2 ? r c c o -------------------- - C 3r 1 ------------------------------------ - = (eq. 31) r 3 3r c r 1 r o 3r c C ---------------------- - = (eq. 32) 1 2 ? r c c o -------------------- - C f s r 1 ------------------------------------------------ - = (eq. 33) r 3 r 1 0.73r o c o f s 1 C ---------------------------------------- = (eq. 34) c 1 r 1 r 3 + ?? c3 2 ? f c r t r 1 c o -------------------------------- - = (eq. 35) r 2 1 4 ? f c c 1 ------------------- = (eq. 36) 0 20 40 60 80 100 120 140 160 180 100 1k 10k 100k 1m frequency (hz) phase margin figure 37. simulated loop bode plot -60 -40 -20 0 20 40 60 80 100 1k 10k 100k 1m d b frequency (hz) loop gain degree ()
isl78201 22 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8615.1 march 31, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback layout suggestions 1. put the input ceramic capacitors as close to the ic vin pin and power ground connecting to the power mosfet or diode. keep this loop (input ceramic capacitor, ic v in pin and mosfet/diode) as tiny as po ssible to achieve the least voltage spikes induced by the trace parasitic inductance. 2. put the input aluminum capacitors close to ic vin pin. 3. keep the phase node copper area small but large enough to handle the load current. 4. put the output ceramic and aluminum capacitors also close to the power stage components. 5. put vias (20 recommended) in the bottom pad of the ic. the bottom pad should be placed in the ground copper plane with an area as large as possible in multiple layers to effectively reduce the thermal impedance. 6. place the 4.7f ceramic decoupling capacitor at the vcc pin and as close as possible to the ic. put multiple vias ( 3) close to the ground pad of this capacitor. 7. keep the bootstrap capacitor close to the ic. 8. keep the lgate drive trace as short as possible and try to avoid using a via in the lgate drive path to achieve the lowest impedance. 9. place the positive voltage sense trace close to the load for tighter regulation. 10. place all the peripheral control components close to the ic. . about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/ask . reliability reports are also available from our website at www.intersil.com/support figure 38. pcb via pattern revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change march 31, 2015 fn8615.1 on page 6, updated charged device mo del test method from ?jesd22-c101e? to ?aec-q100-11?. february 18, 2014 fn8615.0 initial release
isl78201 23 fn8615.1 march 31, 2015 submit document feedback package outline drawing m20.173a 20 lead heat-sink thin shrink small outline package (htssop) rev 0, 8/13 detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burr s. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include inter lead flash or protrusion. inter lead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrus ion shall be 0.80mm total in excess of dimension at maximum materia l condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. 0.09-0.20 see detail "x" 0.90 +0.15/-0.10 0.60 0.15 0 min to 0.15 max plane gauge 0-8 0.25 1.00 ref 20 0.20 c b a 2 1 3 9 b 1 3 10 a pin #1 i.d. mark 6.50 0.10 6.40 4.40 0.10 0.65 0.10 c seating plane 0.25 +0.05/-0.06 5 c h - 0.05 1.20 max 0.10 c b a m 3.00 4.20 exposed thermal pad bottom view (4.20) (1.45) (5.65) 0.6500 (0.35 typ) (3.00)

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